1. Field of the Invention
The present invention relates to increasing the speed and efficiency of a microprocessor while maintaining its compatibility with the instruction set architecture. More particularly, the present invention is a technique for decreasing the amount of processing resources needed to execute particular microprocessor instructions. A xe2x80x9cvirtualxe2x80x9d condition code (VCC) is provided in a non-architected register and is available for use by various instructions that depend upon the occurrence of a specific event. By using the virtual condition code, the programmer visible codes in a flags register, or condition register are unaffected, thereby maintaining compatibility with the instruction set architecture.
2. Description of Related Art
In the computer industry there is a constant demand for ever faster and more efficient systems. Computer processing efficiency is largely dependent on the speed and resource utilization of the microprocessor that controls the basic functions of the computer system. Those microprocessors manufactured by the Intel Corporation execute a specific microprocessor instruction set architecture (ISA). Other Intel (ISA) compatible microprocessors include those manufactured by Advanced Micro Devices, Inc., National Semiconductor and others. These Intel ISA microprocessors command a huge percentage of the marketplace and have caused a correspondingly large amount of software to be written for them. Due to this large amount of Intel ISA software, microprocessor developers cannot change the programmer visible aspects of the instruction set, since it may cause this large quantity of existing software (legacy software) to become inoperable.
Therefore, a challenge to microprocessor developers has been to improve the efficiency of the microprocessor without changing the manner in which the ISA is implemented on the processor. For example, many instructions in the Intel architecture require sub-operations to be performed before the instruction can be completed. If the number of sub-operations, i.e. micro-ops, can be minimized or their performance optimized, without changing the ISA or programmer visible registers, then performance of the microprocessor can be enhanced.
Typically, some instructions in the ISA, such as a LOOP, LOOPcc, REP, REPE, REPNE instruction will decrement a value in a register, such as a general purpose register (GPR) or the like. For example, each time the LOOP instruction is executed a count register is decremented and checked for zero. If the count equals zero, then the loop is terminated and program execution continues with the instruction following the LOOP. When the count is not zero, a jump (branch) is performed to a destination operand or instruction at a target address, usually the first instruction in the loop. The LOOP instruction does not modify the programmer visible condition code(s) in the flags register. The LOOP instruction will decrement a count register (ECX or CX) and then perform a comparison to see if the value is equal to zero. Whether the ECX or CX register is used depends on the size of the address. For 32 bit applications ECX is used and for 16 bit applications CX is used. Thus, the comparison operation will need to check at least 16 and possibly 32 locations which requires significant processing resources, such as hardware logic needed to perform the actual compare function.
The LOOPcc instruction also decrements the ECX/CX register and compares the decremented value to zero, but allows the loop to be exited early by checking a condition code in the flags register. In either case, the compare logic is required to check the decremented value in the ECX/CX register with zero.
The Intel ISA does not allow the flags register to be set/reset by the LOOP, LOOPcc repeat instructions because the software (OS and/or application) would be required to check the condition code in the flags register during each loop. Since the ECX register is 32 bits, a loop could include 232 iterations and place a substantial burden on the software. The CX register is 16 bits and could include 216 iterations.
Further, if the flags register is set/reset during each iteration, the programmer (operating system and/or application) would be forced to save and then restore the register contents for each iteration in the loop.
Thus, in conventional systems there are competing requirements that tend to work against one another. That is, Intel ISA repetitive instructions (LOOP and REP) are not allowed to update and use the more efficient condition codes in the flags register since it would require the program to save/restore after each iteration. Further, by not being allowed to use the condition codes in the flags register, the repetitive instructions must then use less efficient techniques to determine when to exit the loop, i.e. checking the 32 bit ECX register.
Therefore, it can be seen that a need exists for a microprocessor that executes the Intel instruction set architecture and maintains compatibility with software written for the Intel ISA, while efficiently executing those instructions using less hardware resources.
In particular it would be advantageous for a microprocessor to be able to check a condition code, rather than a 32 bit register, to determine whether to exit a set of repetitive instructions. And, at the same time maintaining the program visible condition codes in the flags register to prevent the need for the software to save/restore the register contents after each iteration.
In contrast to the prior art, the present invention utilizes a xe2x80x9cvirtualxe2x80x9d condition code (VCC), stored in an internal, non-architected register, which can control the instruction sequence in a microprocessor.
Broadly, the present invention utilizes a virtual condition code that is not visible to the programmer, but is used by various microprocessor instructions to determine when a branch is to be taken. For example, the virtual condition code can be used as a condition for branching out of a series of repetitive instructions. The virtual condition code (VCC) can eliminate a portion of the processing overhead used when determining whether a sequential number, such as a count value in a register associated with a repetitive instruction, e.g. a LOOP, is zero. In accordance with one aspect of the present invention, a LOOP instruction will decrement a count value in a register (to maintain compatibility with the ISA). However, a corresponding branch instruction will use the virtual condition code, rather than checking the contents of the entire register, to determine whether or not to branch. In this manner, the present invention improves performance by minimizing the amount of hardware resources (i.e. compare logic) utilized while maintaining compatibility with the Intel architecture since the programmer visible condition code is not used. By leaving the programmer visible condition codes unchanged, the software is not forced to save and restore the register contents during each iteration.
Therefore, in accordance with the previous summary, objects, features and advantages of the present invention will become apparent to one skilled in the art from the subsequent description and the appended claims taken in conjunction with the accompanying drawings.